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PRELIMINARY
CY7C1399D
256K (32K x 8) Static RAM
Features
* Pin- and function-compatible with CY7C1399B * Single 3.3V power supply * Ideal for low-voltage cache memory applications * High speed -- tAA = 8 ns * Low active power -- ICC = 60 mA @ 10 ns * Low CMOS standby power -- ISB2 = 1.2 mA ("L" Version only) * Data Retention at 2.0V * Available in 28-SOJ and 28-TSOP I Pb-Free packages
Functional Description[1]
The CY7C1399D is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption when deselected. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399D is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I Pb-Free packages.
Logic Block Diagram
Pin Configurations
SOJ Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
INPUT BUFFER
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
CE WE OE
ROW DECODER
I/O2
SENSE AMPS
32K x 8 ARRAY
I/O3 I/O4 I/O5
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A 10
A 11
A 12 A 13
Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05467 Rev. *C
*
A 14
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 10, 2005
PRELIMINARY
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current L 1399D-10 10 60 3.0 1.2 1399D-12 12 50 3.0 1.2
CY7C1399D
1399D-15 15 40 3.0 1.2 Unit ns mA mA
Pin Configuration
TSOP I Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
Document #: 38-05467 Rev. *C
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[2] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V
CY7C1399D
DC Input Voltage[2] ................................ -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Electrical Characteristics Over the Operating Range
7C1399D-10 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-down Current -- TTL Inputs Automatic CE Power-down Current -- CMOS Inputs[4] GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE VIH, VIN VIH, or VIN VIL,f = fMAX Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +1 -300 60 10 L 10 3.0 1.2 2.0 -0.3 -1 -1 Max. 7C1399D-12 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +1 -300 50 10 10 3.0 1.2 7C1399D-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs[4]
[3]
Max.
Unit V V V V A A mA mA mA mA mA mA
Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V, or VIN 0.3V, L WE VCC - 0.3V or WE 0.3V, f = fMAX Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
Unit V V V V A A mA mA mA mA mA mA
2.0 -0.3 -1 GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE VIH, VIN VIH, or VIN VIL, f = fMAX L -1
VCC +0.3V 0.8 +1 +1 -300 40 10 10 3.0 1.2
Max. VCC, CE VCC-0.3V, VIN VCC - 0.3V, or VIN 0.3V, WEVCC-0.3V or L WE 0.3V, f=fMAX
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Device draws low standby current regardless of switching on the addresses. 5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05467 Rev. *C
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PRELIMINARY
Capacitance[5]
Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 5 6 6
CY7C1399D
Unit pF pF pF
Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All - Packages TBD TBD Unit C/W C/W
AC Test Loads and Waveforms
10-ns Device OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Z = 50 12-ns Device R1 317
30 pF*
3.3V OUTPUT 30pF R2 351
(a)
Equivalent to: THEVENIN EQUIVALENT 167 OUTPUT 1.73V
INCLUDING JIG AND SCOPE
(b)
High-Z characteristics: R1 317
ALL INPUT PULSES 3.0V 10% GND 3 ns 90% 90% 10% 3 ns
3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (c) R2 351
(d)
Switching Characteristics Over the Operating Range [7]
1399D-10 Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[8] OE HIGH to High Z[8, 9] 3 CE LOW to Low Z[8] 0 5 3 3 10 5 0 5 3 100 10 10 3 12 5 0 6 100 12 12 3 15 6 100 15 15 s ns ns ns ns ns ns ns ns Description Min. Max. 1399D-12 Min. Max. 1399D-15 Min. Max. Unit
Notes: 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF.
Document #: 38-05467 Rev. *C
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PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[7]
1399D-10 Parameter tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[10, 11]
CY7C1399D
1399D-12 Min. 0 Max. 6 0 12 12 8 8 0 0 8 7 0 15 10 10 0 0 10 8 0 7 3 3 7 15 1399D-15 Min. Max. 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Description CE HIGH to High Z[8, 9] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[10] WE HIGH to Low Z[8]
Min. 0
Max. 5 10
10 8 7 0 0 7 5 0 7 3
Notes: 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured 200 mV from steady state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05467 Rev. *C
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PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR tR[12]
[5]
CY7C1399D
Conditions Min. 2.0 Max. 3 1.2 0 tRC Unit V mA mA ns ns
Description VCC for Data Retention Data Retention Current Non-L, Com'l / Ind'l L-Version Only Chip Deselect to Data Retention Time Operation Recovery Time
VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2[14, 15]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID tRC
HIGH IMPEDANCE
DATA OUT
Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 16, 17]
tWC ADDRESS CE tAW WE tSA tPWE tHA
CY7C1399D
OE tSD DATA I/O NOTE 18 tHZOE DATAINVALID tHD
Write Cycle No. 2 (CE Controlled)[10, 16, 17]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID tHD tHA tSCE
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 17]
tWC ADDRESS CE tAW WE tSA tHA
tSD DATA I/O NOTE 18 tHZWE
Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in the output state and input signals should not be applied.
tHD
DATA IN VALID tLZWE
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PRELIMINARY
Truth Table
CE H L L L WE X H L H OE X L X H Input/Output High Z Data Out Data In High Z Mode Deselect/Power-Down Read Write Deselect, Output Disabled
CY7C1399D
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1399D-10VXC CY7C1399D-10ZXC CY7C1399DL-10VXC CY7C1399DL-10ZXC CY7C1399D-10VXI CY7C1399D-10ZXI CY7C1399DL-10VXI CY7C1399DL-10ZXI 12 CY7C1399D-12VXC CY7C1399D-12ZXC CY7C1399DL-12VXC CY7C1399DL-12ZXC CY7C1399D-12VXI CY7C1399D-12ZXI CY7C1399DL-12VXI CY7C1399DL-12ZXI 15 CY7C1399D-15VXC CY7C1399D-15ZXC CY7C1399DL-15VXC CY7C1399DL-15ZXC CY7C1399D-15VXI CY7C1399D-15ZXI CY7C1399DL-15VXI CY7C1399DL-15ZXI Package Name V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 Package Type 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) 28-Lead Molded SOJ (Pb-Free) 28-Lead Thin Small Outline Package (Pb-Free) Industrial Industrial Commercial Industrial Industrial Commercial Industrial Industrial Operating Range Commercial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05467 Rev. *C
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PRELIMINARY
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
CY7C1399D
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05467 Rev. *C Page 9 of 10
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY7C1399D 256K (32K x 8) Static RAM (Preliminary) Document Number: 38-05467 REV. ** *A *B *C Ecn No. 201560 233722 262950 307594 Issue Date See ECN See ECN See ECN See ECN Orig. of Change SWI RKF RKF RKF Description of Change Advance Information data sheet for C9 IPP
CY7C1399D
DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the `ordering information Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -10, -12 and -15 ns
Document #: 38-05467 Rev. *C
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